Features
| • | IEEE 1149.1 (JTAG) Compliant |
| • | 2.7V to 3.6V VCC Operation |
| • | TRI-STATE outputs for bus-oriented applications |
| • | Dual byte-wide data for bus applications |
| • | Power down high Impedance inputs and outputs |
| • | Optional Bus Hold on data inputs eliminates the need for external pullup/pulldown resistors (SCANH16512, SCANH162512 versions) |
| • | Optional 25 series resistors in outputs to minimize noise and eliminate termination resistors (SCAN162512, SCANH162512 versions) |
| • | Supports live insertion/withdrawal |
| • | Includes CLAMP and HIGHZ instructions |
Description The SCAN16512 is a high speed, low-power universal bus transceiver featuring data inputs organized into two 8-bit bytes with output enable and latch enable control signals. This function is configurable as a D-type Latch or Flip-Flop, and can operate in transparent, latched, or clocked mode. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and Test Reset (TRST#).
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