DS10BR254 - 1.5 Gbps 1:4 LVDS Repeater

Datasheet Packaging Samples & Pricing Models Knowledge Base

Features
DC - 1.5 Gbps low jitter, low skew, low power operation
Wide Input Common Mode Voltage Range allows for DC-coupled interface to LVDS, CML and LVPECL drivers
Redundant inputs
^LOS circuitry detects open inputs fault condition
Integrated 100Ω input and output terminations
8 kV ESD on LVDS I/O pins protects adjoining components
Small 6 mm x 6 mm LLP-40 space saving package

General Description


The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over FR-4 printed circuit board backplanes and balanced cables. More...


Applications


Clock distribution
Clock and data buffering and muxing
OC-12 / STM-4
SD/HD SDI Routers
  Typical Application
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Parametric Table     expand
Parametric Table    collapse
Temperature Min -40 deg C
Temperature Max 85 deg C
SupplyVoltage 3.3 Volt
Temperature Min -40 deg C
Temperature Max 85 deg C
SupplyVoltage 3.3 Volt
JTAG1149.1 No
Function 1:n Repeater
View Using Catalog


Typical Performance


click for larger image


  Block Diagram
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Datasheet
RoHS Compliance Information Size in KbytesDate Click link below to Download
DS10BR254 1.5 Gbps 1:4 LVDS Repeater 288 Kbytes 14-Apr-08 View Online
Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.


Package Availability, Models, Samples & Pricing
Part NumberPackageFactory Lead TimeModelsSamples &
Electronic
Orders
Budgetary PricingStd
Pack
Size
Package
Marking
Format
TypePinsSpec.MSL
Rating
Peak
Reflow
RoHS
Report
CAD
Symbols
WeeksQtyQty$US each
DS10BR254TSQLLP40NOPB3260RoHS N/A Full production
ds10br254.ibs
Samples
Buy Now
1K+$3.95reel
of
250
NS
UZXYTT
1BR254SQ
6 weeksN/A
DS10BR254TSQXLLP40NOPB3260RoHS N/A Full production
ds10br254.ibs
 
Buy Now
1K+$3.95reel
of
2500
NS
UZXYTT
1BR254SQ
12 weeksN/A

General Description


The DS10BR254 is a 1.5 Gbps 1:4 LVDS repeater optimized for high-speed signal routing and distribution over FR-4 printed circuit board backplanes and balanced cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The device has two different LVDS input channels and a select pin determines which input is active. A loss-of-signal ( ^LOS) circuit monitors both input channels and a unique ^LOS pin is asserted when no signal is detected at that input.

Wide input common mode range allows the switch to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires a minimal space on the board while the flow-through pinout allows easy board layout. Each differential input and output is internally terminated with a 100Ω resistor to lower device return losses, reduce component count and further minimize board space.

Application Notes


TitleSize in Kbytes Date Click link below to Download
AN-1926: Application Note 1926 An Introduction to M-LVDS and Clock and Data Distribution Applications 344 Kbytes 4-Dec-08 Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 7-Jan-2009]