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Power Savings
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Self-refreshed Partial Display Mode
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Provides timing signal for on-glass charge-sharing circuit
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Standard Command Set
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Registers initialized from on-chip EEPROM
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Command-triggered profiles can change register settings for modes/gamma settings
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Eliminates frequent host SW changes to update register settings
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8 user-defined display configurations
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Programmable Settings
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Display resolution and glass signal timing
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Video interface timing auto-learning circuit
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VID_XFR output reduces tearing in partial mode
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Gamma curves and VCOM adjustment
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Advanced Display Features
(evaluation only)
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Configurable Partial Mode Window size, location and color depth
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Self-refreshed partial display mode supports 1–bit and 3–bit depths
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OSD function with Partial RAM data in video mode
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Alpha blending, including transparent mode
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Video 2x upscale with programmable border
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Partial Window 2x upscale with border color
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Interfaces
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Serial Interface (LoSSI) for commands, register access and partial memory access
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24–bit RGB Video interface
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MPL1 high-speed serial interface
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The FPD95120 is a 320–channel LTPS/CGS driver with Partial Display Memory, a 24–bit RGB video interface and enhanced display
quality. More...
RoHS Compliance Information
