LMK01000 - 1.6 GHz High Performance Clock Buffer, Divider, and Distributor

	LMK01000 - 1.6 GHz High Performance Clock Buffer, Divider, and Distributor

Datasheet	Packaging	Samples & Pricing	Eval. Boards	Design Tools	Knowledge Base

Features

30 fs additive jitter (100 Hz to 20 MHz)

Dual clock inputs

Programmable output channels (0 to 1600 MHz)

External synchronization

Pin compatible family of clocking devices

3.15 to 3.45 V operation

Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)

Device	LVDS Outputs	LVPECL Outputs
LMK01000	3	5
LMK01010	8	0
LMK01020	0	8

General Description

The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. More...

Typical Application

*click for larger image

System Diagram

Parametric Table expand

Parametric Table collapse

Max Output Clock Freq 1600 MHz

Additive Jitter 30 ps

LVDS Outputs 3

LVPECL Outputs 5

LVCMOS Outputs 0

Max Output Clock Freq 1600 MHz

Additive Jitter 30 ps

LVDS Outputs 3

LVPECL Outputs 5

LVCMOS Outputs 0

Min Supply Voltage 3.15 Volt

Max Supply Voltage 3.45 Volt

Temperature Min -40 deg C

Temperature Max 85 deg C

PowerWise No

View Using Catalog

Typical Performance

*click for larger image

LVPECL Output Noise Floor

Also Recommended

LMK02000	Clock Jitter Cleaner With External VCXO (LVPECL/LVDS Outputs)
LMK02002	Clock Jitter Cleaner With External VCXO (LVPECL Outputs)
LMK03000C	Clock Jitter Cleaner With Integrated 1.2 GHz VCO (LVPECL/LVDS Outputs)
LMK03001C	Clock Jitter Cleaner With Integrated 1.5 GHz VCO (LVPECL/LVDS Outputs)
LMK03002C	Clock Jitter Cleaner With Integrated 1.7 GHz VCO (LVPECL Outputs)
LMK03033C	Clock Jitter Cleaner With Integrated 2.0 GHz VCO (LVPECL/LVDS Outputs)
LMK04031B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.5 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)
LMK04033B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 2.0 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)
LMK04000B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.2 GHz VCO (LVPECL/LVCMOS Outputs)

Additional Resources

Design Tools (see below)

Block Diagram

*click for larger image

Functional Block Diagram

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
LMK01000 Family 1.6 GHz High Performance Clock Buffer, Divider, and Distributor	502 Kbytes	16-Dec-08	View Online Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

LMK01000EVAL

1.6 GHz Low Noise Clock Buffer, Divider, and Distributor

Preliminary

N/A

$290.00

N/A

LMK01000ISQE

LLP

NOPB

260

RoHS

N/A

Full production

N/A

500+

$8.11

reel
of
250

NS
UZXYTT
K01000 I

12 weeks

N/A

LMK01010ISQE

LLP

NOPB

260

RoHS

N/A

Full production

N/A

500+

$8.11

reel
of
250

NS
UZXYTT
K01010 I

6 weeks

N/A

LMK01000ISQ

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$7.25

reel
of
1000

NS
UZXYTT
K01000 I

6 weeks

N/A

LMK01010ISQ

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$7.25

reel
of
1000

NS
UZXYTT
K01010 I

6 weeks

N/A

LMK01000ISQX

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$7.25

reel
of
2500

NS
UZXYTT
K01000 I

12 weeks

N/A

LMK01010ISQX

LLP

NOPB

260

RoHS

N/A

Full production

N/A

1K+

$7.25

reel
of
2500

NS
UZXYTT
K01010 I

12 weeks

N/A

General Description

The LMK01000 family provides an easy way to divide and distribute high performance clock signals throughout the system. These devices provide best-in-class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners.

The LMK01000 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock domains.

Each device features 8 clock outputs with independently programmable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*).

Design Tools

Title	Size in Kbytes	Date
More design resources for the LMK clock conditoners	19 Kbytes	2-Jun-2008	View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

Title	Size in Kbytes	Date
AN-1864: Application Note 1864 Phase Synchronization with Multiple Devices and Frequencies	150 Kbytes	24-Jun-08	Download
AN-1821: Application Note 1821 CPRI Repeater System	1497 Kbytes	15-May-08	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 7-Jan-2009]