LMK03000 - Precision Clock Conditioner with Integrated VCO

	LMK03000 - Precision Clock Conditioner with Integrated VCO from the PowerWise® Family

Datasheet	Packaging	Samples & Pricing	Design Tools	Models	Application Notes	Knowledge Base

Features

•	Integrated VCO with very low phase noise floor
•	Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz
•	VCO divider values of 2 to 8 (all divides)
•	Channel divider values of 1, 2 to 510 (even divides)
•	LVDS and LVPECL clock outputs
•	Partially integrated loop filter
•	Dedicated divider and delay blocks on each clock output
•	Pin compatible family of clocking devices
•	3.15 to 3.45 V operation
•	Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
•	200 fs RMS Clock generator performance (10 Hz to 20 MHz) with a clean input clock

General Description

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. More...

Typical Application

*click for larger image

Apps Diagram

Parametric Table expand

Parametric Table collapse

Max Output Clock Freq 648 MHz

Min VCO Freq 1185 MHz

Max VCO Freq 1296 MHz

Max Output Clock Freq 648 MHz

Min VCO Freq 1185 MHz

Max VCO Freq 1296 MHz

PLL Type PLL + VCO

RMS Jitter 0.8 ps

LVDS Outputs 3

LVPECL Outputs 5

LVCMOS Outputs 1

Min Supply Voltage 3.15 Volt

Max Supply Voltage 3.45 Volt

Temperature Min -40 deg C

Temperature Max 85 deg C

Power Consumption 1.1797 Watt

PowerWise Rating 6 104.8622222 mW x ps /ch

PowerWise Yes

View Using Catalog

Typical Performance

click for larger image

WEBENCH Live Simulation!

LMK03000 WEBENCH® Design/Analyze/Build It
Custom Design Options (Advanced Options)
Min Output Freq	MHz	>= 1185	help
Max Output Freq	MHz	<= 1296	help
Channel Spacing	KHz	> 0	help
Crystal Freq	MHz	> 0	help
Max Supply	V	> 0	help

What is WEBENCH®

Also Recommended

LMK01000	1.6 GHz Low-Noise Clock Distributor (LVPECL/LVDS Outputs)
LMK02000	Clock Jitter Cleaner With External VCXO (LVPECL/LVDS Outputs)
LMK02002	Clock Jitter Cleaner With External VCXO (LVPECL Outputs)
LMK03000C	Clock Jitter Cleaner With Integrated 1.2 GHz VCO (LVPECL/LVDS Outputs)
LMK03001C	Clock Jitter Cleaner With Integrated 1.5 GHz VCO (LVPECL/LVDS Outputs)
LMK03002C	Clock Jitter Cleaner With Integrated 1.7 GHz VCO (LVPECL Outputs)
LMK03033C	Clock Jitter Cleaner With Integrated 2.0 GHz VCO (LVPECL/LVDS Outputs)
LMK04031B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.5 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)
LMK04033B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 2.0 GHz VCO (LVPECL/LVDS/LVCMOS Outputs)
LMK04000B	Clock Jitter Cleaner With Cascaded PLLs And Integrated 1.2 GHz VCO (LVPECL/LVCMOS Outputs)

Additional Resources

Design Tools (see below)

Application Notes (see below)

Block Diagram

*click for larger image

Functional Block Diagram

Datasheet

RoHS Compliance Information	Size in Kbytes	Date
LMK03000 Family Precision Clock Conditioner with Integrated VCO	653 Kbytes	4-Sep-08	View Online Download
LMK03000 Family Precision Clock Conditioner with Integrated VCO (Japanese)	814 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Package Availability, Models, Samples & Pricing

Part Number

Package

Factory Lead Time

Models

Samples &
Electronic
Orders

Budgetary Pricing

Std
Pack
Size

Package
Marking
Format

Type

Pins

Spec.

MSL
Rating

Peak
Reflow

RoHS
Report

CAD
Symbols

Weeks

Qty

$US each

LMK03000ISQ

LLP

NOPB

260

RoHS

Download

Full production

lmk03000.ibs

1K+

$11.00

reel
of
250

NS
UZXYTT
K03000 I

12 weeks

N/A

LMK03000ISQX

LLP

NOPB

260

RoHS

Download

Full production

lmk03000.ibs

1K+

$11.00

reel
of
2500

NS
UZXYTT
K03000 I

12 weeks

N/A

General Description

The LMK03000 family of precision clock conditioners combine the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The devices integrate a Voltage Controlled Oscillator (VCO), a high performance Integer-N Phase Locked Loop (PLL), a partially integrated loop filter, and up to eight outputs in various LVDS and LVPECL combinations.

The VCO output is optionally accessible on the Fout port. Internally, the VCO output goes through a VCO Divider to feed the various clock distribution blocks.

Each clock distribution block includes a programmable divider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVDS or LVPECL output buffer. This allows multiple integer-related and phase-adjusted copies of the reference to be distributed to eight system components.

The clock conditioners come in a 48-pin LLP package and are footprint compatible with other clocking devices in the same family.

Design Tools

Title	Size in Kbytes	Date
More design resources for the LMK clock conditoners	19 Kbytes	2-Jun-2008	View

If you have trouble printing or viewing PDF file(s), see Printing Problems.

Application Notes

Title	Size in Kbytes	Date
AN-1864: Application Note 1864 Phase Synchronization with Multiple Devices and Frequencies	150 Kbytes	24-Jun-08	Download
AN-1865: Application Note 1865 Frequency Synthesis and Planning for PLL Architectures	147 Kbytes	2-Jul-08	Download
AN-1879: Application Note 1879 Fractional N Frequency Synthesis	511 Kbytes	10-Dec-08	Download
AN-1821: Application Note 1821 CPRI Repeater System	1497 Kbytes	15-May-08	Download

If you have trouble printing or viewing PDF file(s), see Printing Problems.

More Application Notes

Title	Size in Kbytes	Date
AN-1734: Application Note 1734 Using the LMK03000C to Clean Recovered Clocks	188 Kbytes	2-May-08	Download
AN-1734 (Chinese): Application Note 1734 Using the LMK03000C to Clean Recovered Clocks	338 Kbytes

If you have trouble printing or viewing PDF file(s), see Printing Problems.

[Information as of 7-Jan-2009]